1. Introduction

Light detection in standard CMOS technology can be performed by reverse-biased junction diodes. When the diode is illuminated, incident photons with an energy greater than or equal to the bandgap of the semiconductor material generate electron-hole pairs in the depletion region. The carrier pairs are separated by the electric field and drift in opposite directions. The carriers generated outside the depletion region, but within a diffusion length of either side of it, diffuse inward and are collected across the junction. They add a tail to the photodiodes time response because the diffusion process involved is slow.

A good photodetector generates a large photocurrent for a given optical input photon flux given in photon number per cm2sec. To be high, the depletion region must be sufficiently wide to absorb a large fraction of the incident light within the layer. This is also the requirement for a high-speed photodiode, because otherwise slowly diffusing carriers would be generated outside the depletion region. A wide depletion region can be accomplished by increasing the bias voltage or by decreasing the doping in one of the diodes semiconductor materials. However, in a standard CMOS technology, the bias voltage is limited to the maximum power supply, and changing the doping levels is not possible since this would involve changing the process steps and raising the cost.

Figure 1 shows the three junctions of a standard CMOS process which can be used to detect light. Dimensions are not drawn to scale. The first possible photodiode is an n+ to p− substrate junction. A second possibility is to use the n-well to p− substrate junction which has the widest depletion region, because concentration levels of the n-well and the p− substrate are relatively low. The third possibility is the p+ to n-well junction. The first and third junctions are less suitable for detecting light, due to the shallower depletion regions.

Fig. 1. The three junctions of a standard CMOS process which can be used to detect light

In the simulation example, TCAD Studio is used to evaluate an improved CMOS photodiode design shown in Fig. 2a. As indicated, an asymmetric MOSFET with p+ source and N+ drain is placed over the N-well, forming the photodiode with drain contact being the cathode and the source contact being the anode. The main advantage of this photodiode lies in its producing a higher photocurrent for given silicon area owing to the presence of P+/N-well junction depletion region. It will be compared by the TCAD Studio with the photocurrent obtained from simulations of N+/N-well/P-subs photodiode shown in Fig. 2b having identical geometry as the diode in Fig. 2a.

Fig. 2a. Photodiode with asymmetric MOSFET placed inside N-well.

Fig. 2b. Photodiode with conventional N+/N-well/P-subs junction.

2. Simulation results

The inverse photodiode currents are simulated for different cathode voltages assuming monochromatic light l=362nm (absorption coefficient=109cm-1) and two illumination intensities (photon fluxes). The results shown in Fig. 3 does not show an obvious advantage of the new photodiode design (Fig. 2a) over the conventional device (Fig. 2b) in terms of photocurrent magnitude. However, by comparing the generation rates of both structures shown in the 3D plots of Fig. 4, it is obvious that there is an additional photo-generation occurring in the P+/N-well surface junction. This contributes in part to the total photocurrent of the gated photodiode (Fig. 2a) which will be more pronounced in larger area devices.

Fig. 3.  Reverse currents of photodiodes for different photon fluxes.

Fig. 4a. Net doping concentration of the N+/N-well/P-subs photodiode.

Fig. 4b. Carrier generation rates of the N+/N-well/P-subs photodiode.

Fig. 4c. Net doping concentration of gated MOSFET photodiode.

Fig. 4d. Carrier generation rates of gated MOSFET photodiode.